1. Field of the Invention
The present invention relates to a substrate bias potential generator of a semiconductor integrated circuit device and a method therefor and particularly to a construction of a substrate bias potential generator and a method of generating the bias potential, which makes it possible to generate a substrate bias voltage of a desired level reliably with low consumption of power to apply the bias voltage to a semiconductor substrate in a dynamic semiconductor memory device such as a dynamic random access memory (DRAM).
2. Description of the Background Art
Recently, personal computers have become widely popular and used in various fields. Among such personal computers, portable personal computers called lap-top type computers have been lately in great demand. Generally, a portable personal computer uses a battery as an operation power supply and therefore a memory device incorporated therein needs to have low consumption of power. Such a memory device of low consumption of power is for example a dynamic type semiconductor memory device or a static type semiconductor memory device.
Normally, in a semiconductor integrated circuit device including insulated gate field effect transistors (referred to hereinafter as MOSFETs), a substrate bias potential generating circuit is generally provided as shown in FIG. 1 for example.
Referring to FIG. 1, a semiconductor integrated circuit device 500 has MOSFETs and it comprises a function circuit 110 for preforming a predetermined function, and a substrate bias potential generating circuit 120 for generating a predetermined potential V.sub.BB to apply it to a semiconductor substrate 130. Application of the substrate bias potential V.sub.BB makes it possible to reduce parasitic capacitance or the like formed between the semiconductor substrate 130 and the circuit elements such as MOSFETs included in the function circuit 110. In the following, the effect of the substrate bias potential V.sub.BB will be briefly described with reference to FIG. 2.
FIG. 2 shows a sectional structure of a part of the function circuit shown in FIG. 1. In FIG. 2, one MOSFET and an impurity region providing an interconnection region or the like are typically shown. The MOSFET is formed in a predetermined region of a surface of the p type semiconductor substrate 130 and it includes n.sup.+ impurity regions 131 and 132 to be source and drain regions and a gate electrode 133. A gate insulating film 134 is formed between the gate electrode 133 and the p type semiconductor substrate 130. A channel is formed between the source and drain regions 131 and 132 according to the voltage applied to the gate electrode 133. For example, an n.sup.+ impurity region 135 to be a connection region is formed on the surface of the semiconductor substrate 130, with a spacing from the impurity region 131. A signal line 136 is provided through a thick field insulating film 137 on the surface of the semiconductor substrate 130 between the impurity regions 131 and 135. A negative bias potential V.sub.BB is applied to the p type semiconductor substrate 130. The application of the negative potential V.sub.BB makes it possible to reduce a junction capacitance formed by PN junction between the source and drain regions 131 and 132 and the semiconductor substrate 130, as well as a junction capacitance formed by PN junction between the semiconductor connection region 135 and the semiconductor substrate 130. The reduction of the junction capacitances causes a decrease in parasitic capacitance limiting operation speed and thus the integrated circuit device can perform high speed operation.
If a connection 136 for transmitting a signal of an operation power supply voltage level is provided on the field insulating film 137, a channel may be formed between the impurity regions 131 and 135 due to the voltage of the signal line 136, causing formation of a parasitic MOSFET. However, a threshold voltage of the parasitic MOSFET becomes large due to the substrate bias potential V.sub.BB and accordingly it is possible to prevent operation of the parasitic MOSFET, which assures reliable operation of the integrated circuit device.
In addition, an increasing rate of a threshold voltage due to the substrate bias effect of the MOSFET becomes small according to increase of an absolute value of the bias voltage V.sub.BB as well known. Accordingly, even if deviations in characteristics of the circuit elements occur dependent on changes of manufacturing parameters at the time of manufacturing the integrated circuits, it is possible to set the threshold voltage of MOSFETs having such deviations in characteristics to a value of a relatively narrow range by applying the substrate bias potential V.sub.BB, and thus the semiconductor integrate circuit device can be reliably operated.
Furthermore, in the case of transfer gate transistors having memory cell capacitors connected to bit lines in memory cells of DRAMs as shown in FIG. 2, the threshold voltage is increased in the positive direction by the substrate bias potential V.sub.BB and thus leakage current in the transfer gate transistor is decreased. As a result of the decrease of the leakage current in the transfer gate transistor, the charge in the memory cell capacitor can be held for a relatively long period and stable operation of the memory cells is ensured.
The substrate bias generating circuit 120 generates the bias potential V.sub.BB as a result of charge pump operation utilizing the capacitor, as will be clear from the below explanation. The substrate bias potential V.sub.BB is smoothed by a parasitic capacitance and a stray capacitance or the like existing between the semiconductor substrate 130 to which the bias potential is applied and the power supply connection, the semiconductor impurity regions or the like, so that it is maintained at a fixed level.
The above described substrate bias potential V.sub.BB is decreased due to leakage current caused between the semiconductor substrate 130 and the source and drain regions 131 and 132 of the MOSFET or the connection region 135. In other words, the bias potential applied to the semiconductor substrate 132 becomes low. The leakage current in the semiconductor substrate 130 is not always constant and it is affected by the operation of the functional circuit components in the integrated circuit device. The hole current applied to the substrate is relatively small if the MOSFET is in a constant state, that is, held in the on or off state. However, if the MOSFET operates and switching operation is carried out, the positive hole current which is generated in association with circuit operation and flows into the substrate increases accordingly. As a result of generation of the hole current, the absolute value of the substrate bias potential V.sub.BB becomes small. Consequently, in a conventional semiconductor integrated circuit device in general, the substrate bias potential generating circuit is set to have a relatively large current supply capability in order to maintain the substrate bias potential V.sub.BB at the fixed level even if the positive hole current which is generated in associated with circuit operation and flows into the substrate is increased.
In the case of a dynamic type semiconductor memory device of such semiconductor integrated circuit devices, if it is used for a portable personal computer or the like as described above, it is designed to have low consumption of power. In general, in a dynamic semiconductor memory device, its consumption of power is smallest in standby state. In such a standby (in a non-selected state of the semiconductor memory device), consumption of power in a circuit for generating the substrate bias potential V.sub.BB occupies most of the total consumption of power and in order to realize a semiconductor memory device with ultralow standby current, it is necessary to reduce consumption of power in a substrate bias potential generating circuit which operates even in the standby mode.
A method for reducing consumption of power in a substrate bias potential generating circuit as described above is disclosed for example in Japanese Patent Laying-Open Gazette No. 59688/1986, in which two substrate bias potential generating circuits having different bias capabilities (current supply capabilities) are provided and the substrate bias potential generating circuit having the lower capability is constantly operated and the other substrate bias potential generating circuit having the higher capability is intermittently operated dependent on the potential applied to the semiconductor substrate or the operation state of the memory device.
FIG. 3 is a schematic diagram showing the entire construction of a semiconductor memory device comprising a conventional substrate bias potential generating circuit. Referring to FIG. 3, the semiconductor memory device comprises a memory cell array 6 for storing information, and an address buffer 4 for generating an internal address signal upon receipt of external address signals A0 to An. The internal address signal from the address buffer 4 is supplied to the memory cell array 6. The memory cell array 6 decodes the internal address signal in a decoder not shown and selects one or more memory cells in response to the decode signal therefrom. The memory cell array 6 has a matrix arrangement in which generally memory cells of a 1-transistor 1-capacitor type are arranged in rows and columns.
Normally in a dynamic type semiconductor memory device, a row address for designating a row and a column address for designating a column of the memory cell array 6 are multiplexed in a time divisional manner and supplied to the address buffer 4. Therefore, in order to apply timing for accepting the row address and the column address by the address buffer 4, there are an RAS buffer 3 for generating an internal row selection control signal upon receipt of an externally applied row address strobe signal RAS and a CAS buffer 5 for generating an internal column selection control signal upon receipt of an external column address strobe signal CAS. The signal RAS provides timing for accepting the row address signals AO to An by the address buffer 4 and defines a memory cycle of the semiconductor memory device. More specifically, when the signal RAS falls to low (L) level, the storage operation of the semiconductor memory device is started and accessing to the memory cell is effected during the period of L level of the signal RAS. In addition, the signal RAS provides timing for controlling operation of circuits associated with ro selection included in the semiconductor memory device.
The signal CAS applies timing with which the address buffer 4 accepts the column address signal and it also applies operation timing to the circuit related with column selection operation in the semiconductor memory device.
First and second substrate bias potential generating circuits 1 and 2 are provided to apply the bias potential V.sub.BB of the predetermined level to the semiconductor substrate where the semiconductor memory device is formed. The first substrate bias potential generating circuit 1 has a relatively small current supply capability (bias capability) and it constantly operates to generate the substrate bias potential to supply to the semiconductor substrate.
The second substrate bias potential generating circuit 2 operates when the bias potential applied to the semiconductor substrate becomes smaller than the predetermined level (that is, the bias becomes low) in an operation of the memory device, and it applies the bias potential of the predetermined level to the semiconductor substrate. The second substrate bias potential generating circuit has a relatively large current supply capability (bias capability).
FIG. 4 shows an example of specific constructions of the first and second substrate bias potential generating circuits 1 and 2 shown in FIG. 3. Referring to FIG. 4, the first substrate bias potential generating circuit 1 comprises a ring oscillator 11, inverters 12 and 12,, a capacitor 13 and n channel MOSFETs 14 and 15. The ring oscillator 11 is formed by an odd number of stages of inverters for example and its output is fed back to its input to generate a pulse signal of a predetermined frequency. The inverters 12 and 12' wave-shape and amplify the output of the ring oscillator 11 and provide an output. The capacitor 13 couples capacitively the output of the inverter 12 to a node N.sub.A and carries out charge pump operation for generating the bias potential by charging and discharging operation thereof.
The MOSFET 14 has its gate and drain connected to the node N.sub.A and its source connected to the ground potential. The source and the drain of the MOSFETs are defined by polarity of the voltage applied thereto. In the following, the respective nodes are simply defined as the source and drain for convenience of explanation. The MOSFET 14 has a threshold voltage V.sub.T2 and clamps the potential of the node N.sub.A to the threshold voltage.
The MOSFET 15 has its drain connected to the node N.sub.A and its gate and source connected to the bias potential output terminal 9. The MOSFET 15 has a threshold voltage V.sub.T1 and clamps the potential of the node N.sub.A to V.sub.BB -V.sub.T1.
In the case of a construction in which the substrate bias potential is generated in response to the pulse signal from the ring oscillator 11, the current supply capability of the substrate bias potential generating circuit 1 is defined by the oscillation frequency of the ring oscillator 11, the capacitance value of the charge pump capacitor 13 and the conductance of the MOSFET 15. In other words, the charge amount injected into the semiconductor substrate 10 in response to one oscillation output pulse becomes large as the capacitance value of the capacitor 13 becomes large. The number of injections of charge into the semiconductor substrate per unit time becomes large as the oscillation frequency of the ring oscillator 11 becomes large. The substrate bias potential generating circuit 1 which constantly operates is structured to have low power consumption characteristics while maintaining the relatively small current supply capability. More specifically, the oscillation frequency of the ring oscillator 11 is made to have a relatively small value by setting the number of stages of the inverter circuit of the ring oscillator 11 to a suitable value and setting the signal delay characteristic in each inverter circuit suitably. The capacitance value of the capacitor 13 is also set to a relatively small value.
Consumption of power in the ring oscillator 11 is proportional to its oscillation frequency. More specifically, the operation current or consumption current of the inverter circuit (of the CMOS structure) of the ring oscillator 11 is proportional to so-called transient current required for charging and discharging of load capacitance (formed by a connection capacitance or an input capacitance of the inverter circuit of the subsequent stage, or the like) coupled to the output of each inverter circuit, in the same manner as in the case of a CMOS inverter circuit as well known. Accordingly, in a still state in which the input or output of each inverter circuit is fixed to high (H) level or low (L) level, the consumption of current in the ring oscillator 11 is substantially 0. Since the transient current of each inverter circuit is proportional to each operation frequency during oscillation operation, the consumption of power of the ring oscillator 11 having the small oscillation frequency is decreased accordingly. The current supply capability of the inverter 12 as an output buffer for driving rectifier circuit (the capacitor 13, the MOSFETs 14 and 15; analog circuit) is relatively small since the capacitance value of the capacitor 13 is relatively small.
The second substrate bias potential generating circuit 2 which operates intermittently dependent on the potential of the semiconductor substrate or the operation state of the memory device comprises: a ring oscillator 21 which carries out oscillation operation intermittently; inverters 23 and 24 for wave-shaping and amplifying the output of the ring oscillator 21; a charge pump rectifying circuit for rectifying the output of the inverter 24 and applying the rectified output to the semiconductor substrate; a substrate bias potential generating circuit 28 for detecting the potential of the semiconductor substrate and controlling the oscillation operation of the ring oscillator 21 according to the detected potential; and a NOR gate 29. The ring oscillator 21 includes inverters Il and I2 and a NOR gate 22. The number of stages of inverters of the ring oscillator 21 is selected suitably according to the oscillation frequency and the delay characteristics. In this case, for simplification of the illustration, an example of a ring oscillator including three inverters, i.e., two inverters Il and I2 and one NOR gate 22 is shown. The output of the NOR gate 22 is fed back to the input of the inverter Il and is transmitted to the input of the inverter 23. The NOR gate 22 has its one input receiving the output of the inverter I2 and its other input receiving a control signal NC from the NOR gate 29.
Inverters 23 and 24, a capacitor 25 and n channel MOSFETs 26 and 27 are provided to perform the same function as that of the first substrate bias potential generating circuit. The capacitor 25 carries out charge pump operation according to the output of the inverter 24, and the n channel MOSFETs 26 and 27 clamp the potential of the node N.sub.P at a predetermined potential. The MOSFET 26 has a threshold voltage V.sub.T3 and the MOSFET 27 has a threshold voltage V.sub.T4.
The substrate potential detecting circuit 28 is connected to the semiconductor substrate through a bias potential output terminal 9 and it determines whether the potential of the semiconductor substrate is a predetermined value or not and outputs a signal N.sub.D according to the result. The signal N.sub.D is set to H level when the potential of the semiconductor substrate is smaller than a predetermined level in terms of an absolute value to cause the substrate bias potential to be low, and it is set to L level when the substrate potential is larger than the predetermined level in terms of an absolute value.
The NOR gate 29 has its one input terminal for receiving a signal RAS indicating the operation state of the semiconductor memory device from the RAS buffer 3 and its other input terminal for receiving the control signal N.sub.D from the substrate potential detecting circuit 28 to output a control signal N.sub.C. Accordingly, the control signal N.sub.C is set to L level if either the signal RAS or the signal N.sub.D rises to H level, whereby the ring oscillator 21 is activated to perform oscillating operation. When the control signal N.sub.C is at H level, the output of NOR gate 22 is fixed to L level and accordingly the ring oscillator 21 does not perform oscillating operation and no bias potential is provided from the substrate bias potential generating circuit 2. As described above, the bias capability (the current supply capability) of the substrate bias potential generating circuit 2 is defined by the oscillation frequency of the ring oscillator 21 and the capacitance value of the charge pump capacitor 25. Since the bias capability of the substrate bias potential generating circuit 2 is relatively large, the oscillation frequency of the ring oscillator 21 and the capacitance value of the capacitor 25 are respectively large.
FIG. 5 is a diagram showing an example of a construction of the substrate bias potential detecting circuit shown in FIG. 4. Referring to FIG. 5, the substrate potential detecting circuit 28 comprises a p channel MOSFET 281 and n channel MOSFETs 282 and 283, which are connected in series between the operation power supply potential Vcc and the substrate potential V.sub.BB. The p channel MOSFET 281 has its drain connected to the power supply potential Vcc, its gate connected to the ground potential and its source connected to a node N1. The n channel MOSFET 282 has its drain connected to the node N1, its gate connected to the ground potential and its source connected to a node N2. The n channel MOSFET 283 has its drain and gate connected to the node N2 and its source connected to the substrate potential V.sub.BB. The MOSFETs 282 and 283 have threshold voltages V.sub.T5 and V.sub.T6, respectively. Inverters 284 and 285 are provided to wave-shape and amplify the output of the node N1. The output of the inverter 285 is the signal N.sub.D indicating the result of detection of the substrate potential. The p channel MOSFET 281 is constantly in the on state since a signal of the ground potential level is applied to its gate. If the substrate potential V.sub.BB is EQU V.sub.BB &gt;-(V.sub.T5 +V.sub.T6),
the MOSFET 282 is in the non-conductive state and accordingly the potential level of the node N1 is H level. Since the potential level of the node Nl is outputted through the inverters 284 and 285, the output signal N.sub.T in this case is at H level.
If the substrate potential V.sub.BB is EQU V.sub.BB .ltoreq.-(V.sub.T5 +V.sub.T6),
the N channel MOSFET 282 is in the conductive state. In this case, if a ratio of the sizes of the MOSFETs 282 and 282 is suitably selected and the on resistance values thereof are set to a suitable ratio, the level of the node N1 can be set to a level determined to be L by the inverter 284. The control signal N.sub.D in this case is at L level.
In the substrate potential detecting circuit 28, if the MOSFETs 282 and 283 are in the on state, current flows from the power supply potential Vcc to the substrate bias potential V.sub.BB. More specifically, if the semiconductor substrate is of the p type, the substrate bias potential V.sub.BB is set to a negative potential and, also if the semiconductor substrate is in the n type, the bias potential V.sub.BB is set to a positive value smaller than the operation power supply potential Vcc. In such a case, when the MOSFETs 282 and 283 are both in the on state, current flows from the operation power supply potential Vcc to the semiconductor substrate, with the result that the bias potential level of the semiconductor substrate becomes small in terms of an absolute value, making it impossible to carry out detection of the substrate bias potential correctly. Accordingly, in order to minimize the current flowing to the semiconductor substrate through the substrate potential detecting circuit, the conductance of the MOSFET 281 is set to a very small value, so that only small current flows in the MOSFET 282.
FIG. 6 is a waveform diagram showing operation of the substrate bias potential generating circuit shown in FIGS. 4 and 5. Referring to FIG. 6, the signal RAS indicates a row address strobe signal applied to the RAS buffer 3 of FIG. 3, indicating whether the semiconductor memory device is selected to be in operation state or not. V.sub.A and V.sub.B in (b) and (c) of FIG. 6 indicate potentials of nodes N.sub.A and N.sub.B in FIG. 4, respectively. In the following, operation of the conventional substrate bias potential generation circuit will be described with reference to FIGS. 3 to 6.
First, operation of the first substrate bias potential generating circuit 1 will be described. When the pulse signal from the ring oscillator 11 rises to the power supply potential Vcc level and the output level of the inverter 12 is accordingly raised to the power supply potential Vcc, the potential of the node N.sub.A tends to be raised to the power supply potential Vcc due to the capacitance coupling of the capacitance 13. However, when the potential of the node N.sub.A rises to the level of the threshold voltage V.sub.T2 of the MOSFET 14, the MOSFET 14 is conducted and further increase of the voltage is suppressed. As a result, the potential of the node N.sub.A is maintained at the level V.sub.T2. In the meantime, the capacitor 13 is charged by the output of the inverter 12. The MOSFET 15 is in the off state.
When the output of the ring oscillator 11 is lowered to the ground potential level and the output of the inverter 12 is accordingly lowered to the ground potential level, the potential of the node N.sub.A tends to be lowered to the level (V.sub.T2 -Vcc) due to the capacitance coupling of the capacitor 13. However, when the potential of the node N.sub.A becomes smaller than the potential (V.sub.BB -V.sub.T1) obtained by subtraction of the threshold voltage V.sub.T1 of the MOSFET 15 from the substrate potential V.sub.BB, the MOSFET 15 is turned on and electrons are injected into the substrate through the MOSFET 15 in the on state, causing the potential of the substrate to be lowered. As a result, the potential of the node N.sub.A becomes a potential according to the substrate potential.
By repeating the above described operation, electrons are injected into the semiconductor substrate from the terminal 9 through the charge pump capacitor 13, to lower the substrate potential. The degree of lowering of the substrate potential caused by one electron injection operation, namely, one pulse from the ring oscillator 11 is determined by a ratio between the capacitance of the capacitance 13 and the load capacitance of the semiconductor substrate. By repeating the above described operation several times, the potential of the node N.sub.A changes as oscillation between the potential (V.sub.T2 -Vcc) and the potential V.sub.BB of the substrate finally becomes close to the potential (V.sub.T2 -Vcc+V.sub.T1). More specifically, the first substrate bias potential potential generating circuit 1 applies the bias potential determined by the threshold voltages of the two MOSFETs 14 and 15 and the operation power supply potential.
Next, operation of the second substrate bias potential generating circuit 2 will be described. Now let us assume a case in which the semiconductor memory device is selected and is in operation state. In this case, the signal RAS falls to L level and the signal RAS rises to H level. As a result, the NOR gate 29 outputs the control signal N.sub.C of L level independent of the level of the signal N.sub.D indicating the detection result from the substrate potential detecting circuit 28. Since the NOR gate 22 receives the signal of L level at its other input terminal, it operates as an inverter and as a result the ring oscillator 21 starts oscillation operation. The operation of the capacitor 25 and the MOSFETs 26 and 27 is the same as the operation of the capacitor 13 and MOSFETs 14 and 15 included in the first substrate bias potential generating circuit 1. Thus, the charge pump operation of the capacitor 25 and the clamp operation of the MOSFETs 26 an 27 cause injection of electrons into the semiconductor substrate through the terminal 9. Since the bias capability of the second substrate bias potential generating circuit is larger than that of the first substrate bias potential generating circuit, compensation is made for decrease of the value of the substrate bias potential V.sub.BB in terms of the absolute value due to the substrate current of a considerable amount flowing in the operation of the device, whereby the substrate potential is maintained at the predetermined level.
Next, let us assume a case in which the signal RAS is at H level and the signal N.sub.D outputted from the substrate potential detecting circuit 28 is at L level. More specifically, the semiconductor memory device is in a non selected state such as a standby state and the potential of the semiconductor substrate is biased to a predetermined biased value. In this case, the signals applied to the two inputs of NOR gate 29 are both at L level and the output signal N.sub.C from the NOR gate 29 is at H level. As a result, the NOR gate 22 receives the signal of H level at its other input and the output therefrom is at a fixed level of L level. Consequently, the ring oscillator 21 does not carry out oscillating operation.
If the signal RAS is at H level and leakage current flows in the semiconductor substrate due to generation of holes by any cause such as impact ionization to cause the bias potential of the semiconductor substrate to be low (namely, the substrate bias potential V.sub.BB to be smaller in terms of the absolute value), the output signal N.sub.D from the substrate potential detecting circuit 28 rises to H level. As a result, the output signal N.sub.C from the NOR gate 29 falls to L level and the NOR gate 22 operates as an inverter. Consequently, the ring oscillator 21 starts oscillating operation, whereby the potential of the semiconductor substrate is lowered to a predetermined potential level rapidly by its large bias capability.
As described above, in the conventional substrate bias potential generating circuit, two bias potential generating circuits having different bias capabilities are provided and the substrate bias potential generating circuit having the smaller bias capability is constantly operated, while the substrate bias potential generating circuit having the larger bias capability is operated only in the case in which the bias potential of the substrate becomes small in terms of the absolute value and the bias becomes low, thereby to rapidly lower the substrate potential V.sub.BB. Thus, consumption of power in the substrate bias potential generating circuits can be reduced.
However, in the above described construction, if the semiconductor memory device, which is a semiconductor integrated circuit device, is selected to be in operation state, the two substrate bias potential generating circuits both operate, resulting in increase of consumption of power in those substrate bias potential generating circuits.
The construction of the substrate potential detecting circuit enabling the substrate bias potential generating circuit to operate intermittently is the construction as shown in FIG. 5, in which the potential of the substrate is detected by utilizing the threshold voltages of the MOSFETs. Accordingly, in the case of the construction in which the MOSFETs are connected in series between the operation power supply potential Vcc and the semiconductor substrate potential V.sub.BB, when the substrate bias potential V.sub.BB becomes larger than the predetermined potential in terms of the absolute value and the MOSFETs 282 and 283 are turned on, current flows from the operation power supply Vcc to the semiconductor substrate, causing the bias of the semiconductor substrate to be low. As a result, the substrate potential detecting circuit itself causes change in the substrate bias potential and the substrate potential cannot be detected correctly. More specifically, if the bias of the semiconductor substrate becomes low, the second substrate potential generating circuit having the larger bias capability is operated; however, in this case, when the bias potential of the semiconductor substrate attains the predetermined value, the substrate potential detecting circuit provides a path enabling current to flow into the semiconductor substrate, causing the bias of the semiconductor substrate to be shallow and as a result the semiconductor bias potential generating circuit having the larger bias capability is operated unnecessarily. Thus, the substrate potential cannot be detected correctly and consumption of power cannot be reduced.